Designing a 4x4 Wallace tree multiplier circuit using reversible logic in QCA technology

Articles in Press

Document Type : Computer Article

Authors

1 Department of Computer Engineering, Rafsanjan Branch, Islamic Azad University, Rafsanjan, Iran

2 Master's student, Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

Abstract

Quantum-dot Cellular Automata (QCA) technology, due to its unique structure, ultra-low power consumption, and high operating speed, has emerged as a promising alternative to semiconductor transistors. This research aims to design and implement a reversible 4×4 Wallace tree multiplier with optimized propagation delay, speed, and hardware resource usage. In this regard, a reversible 4:2 compressor along with reversible half and full adders within the QCA technology were employed. The proposed design was simulated using the QCA Designer tool, demonstrating that the multiplier consists of approximately 50 quantum cells, with a latency of four clock phases and an approximate area of 0.15 µm². Compared to previous designs, it achieves nearly 20% improvement in speed and approximately 30% reduction in power consumption. The key innovation lies in the use of reversible logic and a 4:2 compressor to reduce delay and energy consumption while maintaining high multiplier performance in QCA technology, thereby achieving an optimal balance among speed, power consumption, and circuit area.

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Main Subjects

Journal of Modeling in Engineering

Articles in Press, Accepted Manuscript
Available Online from 08 November 2025

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History

  • Receive Date: 05 June 2024
  • Revise Date: 30 October 2025
  • Accept Date: 03 November 2025

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