Quantum-dot Cellular Automata (QCA) technology, due to its unique structure, ultra-low power consumption, and high operating speed, has emerged as a promising alternative to semiconductor transistors. This research aims to design and implement a reversible 4×4 Wallace tree multiplier with optimized propagation delay, speed, and hardware resource usage. In this regard, a reversible 4:2 compressor along with reversible half and full adders within the QCA technology were employed. The proposed design was simulated using the QCA Designer tool, demonstrating that the multiplier consists of approximately 50 quantum cells, with a latency of four clock phases and an approximate area of 0.15 µm². Compared to previous designs, it achieves nearly 20% improvement in speed and approximately 30% reduction in power consumption. The key innovation lies in the use of reversible logic and a 4:2 compressor to reduce delay and energy consumption while maintaining high multiplier performance in QCA technology, thereby achieving an optimal balance among speed, power consumption, and circuit area.