In recent years, with the advancement of technology, the design of low-power circuits with minimal area has gained significant attention. Researchers have been seeking structures that enable the design and implementation of low-power electronic systems. Reversible logic has emerged as a promising and practical technology, particularly applicable in low-power CMOS systems and quantum computing. One of the most critical aspects of electronic circuit design is power consumption. Reversible logic, due to its ability to preserve and recover input data, has been proposed as a solution to mitigate energy dissipation. Moreover, it offers additional advantages such as increased circuit speed, reduced quantum cost, decreased garbage outputs, reduced circuit depth, and extended hardware lifespan. In this paper, a reversible Carry Look-Ahead Adder is proposed, employing reversible gates such as NOT, TR, Feynman, and Peres to achieve an optimized design. Comparative analysis shows that the proposed 4-bit adder outperforms existing works in reducing the number of constant inputs. Overall, with an equal quantum cost to comparable designs, the proposed approach achieves a 46% reduction in constant inputs. It is worth noting that the proposed design has also been implemented on FPGA using the VHDL hardware description language and the Xilinx Vivado toolchain.