Design and simulation of Penternary adder based on GNRFET

Document Type : Power Article

Authors

1 Department of

2 Department of Electrical and engineering, Islamic Azad Yazd university, Yazd branch, Yazd, Iran.

Abstract

In this paper, the design of penternary circuits based on graphene nanoribbon FET (GNRFET) is presented. The employed logic of the penternary corresponds to the Galois logic. The HSPICE-compatible model and 15-nanometer technology have been used to simulate the graphene nanoribbon transistor. Accordingly, the proposed NAND and NOR penternary circuits are first, designed and simulated. The results show that these proposed circuits have a significant improvement in terms of speed and power consumption compared to their CNTFET counterparts. Then, the adder circuit as the main part of digital processors in integrated circuit design is proposed with penternary logic. The transient responses of the proposed circuits are accurate. Parameters such as power consumption,, delay and power-delay product are calculated. Evaluation of the results shows that the proposed adder circuit has the power-delay product (PDP) of 179.39 fJ at the supply voltage of 0.8 V and the operating frequency of 100 MHz.

Keywords

References

 
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Journal of Modeling in Engineering
Volume 18, Issue 63
December 2020
Pages 41-50

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History

  • Receive Date: 12 May 2020
  • Revise Date: 17 September 2020
  • Accept Date: 12 October 2020

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