Synthesis Optimization of Arithmetic Circuits on Coarse-Grain Reconfigurable Architecture

Document Type : Computer Article

Authors

1 Assistant Professor Of Department of Computer Hardware Engineering @ Faculty of Electrical & Computer Engineering

2 Researcher

3 Professor Department of Computer Engineering Computer Architecture

Abstract

The increasing capabilities of integrated circuits and the complexity of applications have led hardware design methods and tools to higher levels of abstraction. High-level synthesis is one of the key steps in increasing the level of abstraction, and the more concise the initial description in the intended application, the more efficient the high-level synthesis will be. Arithmetic applications are among the applications in which the initial input is very abstract. In recent years, extensive research has been conducted on the design of arithmetic reconfigurable architectures. Since, on the one hand, the effective use of these architectures depends on the existence of appropriate algorithms and tools to implement the design on the hardware, and on the other hand, research on the development of these algorithms has been very limited, this paper will present methods for optimizing the automated synthesis of arithmetic circuits on a coarse-grained reconfigurable architecture. These optimizations include mapping optimization, delay optimization, and area optimization. The platform chosen to execute the proposed algorithm is the DARA coarse-grained reconfigurable architecture, which is optimized for decimal arithmetic. The results show that implementing the TELCO benchmark on DARA using proposed optimizations entails about 30% gain in the area of the circuit.

Keywords

References

[1] M. Sedighi, F. Haddadi, S. Emami, and M. Saffarpour, “A Heuristic Algorithm for High Level Synthesis of Decial Arithmetic Circuits Using SystemC,” 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015, pp. 1-6.
[2] D. D. Gajski, and L. Ramachandran, “Introduction to High-Level Synthesis,” IEEE Design & Test of Computers, vol.  11, no. 4, 1994, pp.  44-54.
[3] P. Coussy, D. D. Gajski, M. Meredith, and A. Takach, “An Introduction to High-Level Synthesis,” IEEE Design & Test of Computers, vol. 26, no. 4, 2009, pp. 8-17.
[4] R. Nane, V. M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y. T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, and K. Bertels, “A Survey and Evaluation of FPGA High-Level Synthesis Tools,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35 ,  no. 10, 2016, pp. 1591-1604.
[5] L. K. Wang, M. A. Erle, C. Tsen, E. M. Schwarz, and M. J. Schulte, “A Survey of Hardware Designs for Decimal Arithmetic,” IBM Journal of Research and Development, vol. 54, no. 2, 2010, pp. 8:1-8:15.
[6] A. Nannarelli, “FPGA Based Acceleration of Decimal Operations,” International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 146-151.
[7] J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers, and Z. Zhang, “High-Level Synthesis for FPGAs: From Prototyping to Deployment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 4, 2011, pp. 473-491.
[8] M. A. Shami, “Dynamically Reconfigurable Resource Array,” Ph.D. Dissertation, KTH Sch. Inf. Tech. Sweden, Kista, 2012.
[9] Y. Kim, R. N. Mahapatra, and K. Choi, “Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 10, 2010, pp. 1471-1482.
[10] S. Emami, and M. Sedighi, “An Optimized Reconfigurable Architecture for Hardware Implementation of Decimal Arithmetic,” Computers & Electrical Engineering, vol. 63, 2017, pp. 18-29.
[11] M. Vladutiu, “Functional Analysis and Synthesis of Binary and Decimal Adding and Subtracting Devices”, Computer Arithmetic Algorithms and Hardware Implementations, Springer Berlin Heidelberg, 2012.
[12] I. D. Castellanos, “Analysis and Implementation of Decimal Arithmetic Hardware in Nanometer CMOS technology”, Ph.D. Dissertation, Oklahoma State University, USA, 2008.
[13] J. P. Deschamps, G. J. A. Bioul, and G. D. Sutter, “Synthesis of Arithmetic Circuits- FPGA, ASIC and Embedded Systems”, Wiley-Interscience, 2006.
[14] M. A. Gladshtein, “Algorithmic synthesis of a combinational adder of decimal digits encoded by the Johnson-Mobius code”, Automatic Control and Computer Sciences, vol. 43, no. 5, 2009, pp. 233–240.
[15] R. Zimmermann, “Datapath Synthesis for Standard-Cell Design”, Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009, pp. 207-211.
[16] C. K. Cheng, “Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders”, Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009, pp. 212-212.
[17] A. K. Verma, P. Brisk, and P. Ienne, “Challenges in automatic optimization of arithmetic circuits”, Proceedings of the 16th IEEE Symposium on Computer Arithmetic, 2009, pp. 213-218.
[18] X. Liu, C. Yang, and Z. Guan, “Efficient arithmetic expression optimization with weighted  adjoint matrix,” 2020 IEEE 39th International Performance Computing and Communications Conference (IPCCC), 2020, pp. 1-8.
[19] K. E. Murray, J. Luu, M. J. P. Walker, C. McCullough, S. Wang, S. Huda, B. Yan, C. Chiasson, K. B. Kent, J. Anderson, J. Rose, and V. Betz, “Optimizing FPGA Logic Block Architectures for Arithmetic,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 6, 2020, pp. 1378-1391.
[20] بهرام عزیزالله گنجی و صدیقه بابایی صداقت، "بهینه‌سازی ساختار میکروفن خازنی جدید با دیافراگم قورباغه‌ای جهت افزایش حساسیت و کاهش ولتاژ تغذیه"، نشریه مدل‌سازی در مهندسی، دوره 17، شماره 59، زمستان 1398، صفحه 151- 141.
[21] امین رضایی‌پناه، علی مبارکی و سعید بحرانی خادمی، "بهینه‌سازی شبکه عصبی MLP با استفاده از الگوریتم ژنتیک موازی FinGrain برای تشخیص سرطان سینه"، نشریه مدل‌سازی در مهندسی، دوره 17، شماره 57، تابستان 1398، صفحه 186- 173.
[22] مهدی یعقوبی و مرتضی زاهدی، "بهینه‌سازی در همروندی فرآیندهای کسب‌وکار با هدف تعادل بار کاری"، نشریه مدل‌سازی در مهندسی، دوره 17، شماره 57، تابستان 1398، صفحه 172- 159.
Journal of Modeling in Engineering
Volume 20, Issue 69
May 2022
Pages 1-15

Files

History

  • Receive Date: 03 December 2020
  • Revise Date: 10 June 2021
  • Accept Date: 20 November 2021

Share

How to cite

Statistics