In this paper, a novel heterostructure junctionless tunnel field effect transistor with silicon-on-nothing technology (SON HS-JLTFET) is proposed. The proposed device has two advantages over conventional JLTFET. First, one decade of increment in the ON current is achieved and subthreshold swing is improved by 10%. In this device, InAs is used in the source region of SON HS-JLTFET which has a lower energy band gap than Si to achieve thinner tunneling barrier width. Hence, more electron can tunnel from source to channel. As a result, it provides improvements in drain current and subthreshold swing. The second advantage is that the ambipolar current reduction due to the use of SON technique. In fact, in this technique, air is considered as the gate dielectric which results in decrement in the electric field in the drain/channel junction. This reduced electric field causes increasing the width of the tunneling barrier which results in lower ambipolar current in the drain/channel junction.
Vanak, A., & Amini, A. (2024). Designing Heterostructure Junctionless Tunnel Field Effect Transistor with Silicon-on-nothing Technology for DC parameter improvement. Journal of Modeling in Engineering, 22(76), 45-53. doi: 10.22075/jme.2023.29572.2392
MLA
Amin Vanak; Amir Amini. "Designing Heterostructure Junctionless Tunnel Field Effect Transistor with Silicon-on-nothing Technology for DC parameter improvement". Journal of Modeling in Engineering, 22, 76, 2024, 45-53. doi: 10.22075/jme.2023.29572.2392
HARVARD
Vanak, A., Amini, A. (2024). 'Designing Heterostructure Junctionless Tunnel Field Effect Transistor with Silicon-on-nothing Technology for DC parameter improvement', Journal of Modeling in Engineering, 22(76), pp. 45-53. doi: 10.22075/jme.2023.29572.2392
VANCOUVER
Vanak, A., Amini, A. Designing Heterostructure Junctionless Tunnel Field Effect Transistor with Silicon-on-nothing Technology for DC parameter improvement. Journal of Modeling in Engineering, 2024; 22(76): 45-53. doi: 10.22075/jme.2023.29572.2392
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