A New Heterostructure Junctionless Tunnel Field Effect Transistor with Silicon-on-Nothing Technique for DC Parameter Improvement

Document Type : Power Article

Authors

1 Doctoral student, Department of Electrical Engineering, College of Technical and Engineering, West Tehran Branch, Islamic Azad University, Tehran, Iran.

2 Associate Professor, Department of Electrical Engineering, College of Technical and Engineering, West Tehran Branch, Islamic Azad University, Tehran, Iran.

Abstract

In this paper, a novel heterostructure junctionless tunnel field effect transistor with silicon-on-nothing technology (SON HS-JLTFET) is proposed. The proposed device has two advantages over conventional JLTFET. First, one decade of increment in the ON current is achieved and subthreshold swing is improved by 10%. In this device, InAs is used in the source region of SON HS-JLTFET which has a lower energy band gap than Si to achieve thinner tunneling barrier width. Hence, more electron can tunnel from source to channel. As a result, it provides improvements in drain current and subthreshold swing. The second advantage is that the ambipolar current reduction due to the use of SON technique. In fact, in this technique, air is considered as the gate dielectric which results in decrement in the electric field in the drain/channel junction. This reduced electric field causes increasing the width of the tunneling barrier which results in lower ambipolar current in the drain/channel junction.
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Keywords

Main Subjects

References

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Journal of Modeling in Engineering
Volume 22, Issue 76
May 2024
Pages 45-53

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History

  • Receive Date: 11 January 2023
  • Revise Date: 18 July 2023
  • Accept Date: 03 September 2023

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