Design and Simulation of a High-speed, Low-power, Dynamic Double-edge-triggered Flip-flop

Articles in Press

Document Type : Research Paper

Authors

1 Assistant Professor, Biomedical Engineering Department, Hamedan University of Technology, Hamedan, 65169-13733, Iran

2 Department of Basic Sciences, Hamedan University of Technology, Hamedan

Abstract

Given the general trade-off between high-speed operation and low power consumption in digital integrated circuits, simultaneous reduction of the propagation delay and power dissipation in bistable memory elements represents a challenging task. Design of a dynamic dual-edge-triggered flip flop (DETFF) is presented which is faster, employs fewer transistors, and consumes less power than the standard static, master-slave flip flop. The proposed topology for the dynamic DETFF combines a pair of single-edge-triggered flip flops (FFs) using a 2:1 multiplexer with one flip flop being triggered on the positive edge and the other on the negative edge of a true single-phase clock (TSPC). The use of only eight clocked transistors accounts for the low-power operation of the proposed DETFF. The performance of the proposed DETFF is compared with that of a static, master-slave D-type flip-flop in a 90nm CMOS technology based on SPICE simulations. Also, SPICE simulations indicate that operating with a 0.9-V power supply at a clock frequency of 16.7 GHz, the proposed DETFF exhibits an average clock-to-Q delay of 25 ps and consumes 146 µW in a 22nm CMOS technology. The performance of the proposed DETFF is also compared with those of a static DETFF employing C-elements and a static TSPC DETFF capable of near-threshold operation in nanometer CMOS technologies.

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Journal of Modeling in Engineering

Articles in Press, Accepted Manuscript
Available Online from 05 January 2025

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History

  • Receive Date: 18 July 2022
  • Revise Date: 17 March 2024
  • Accept Date: 30 November 2024

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