Design and Simulation of a High-Speed, Low-Power, Dynamic Double-Edge-Triggered Flip-Flop

Document Type : Research Paper

Authors

1 Biomedical Engineering Department, Hamedan University of Technology, Hamedan, Iran

2 Basic Science Department, Hamedan University of Technology, Hamedan, Iran

Abstract

Given the general trade-off between high-speed operation and low power consumption in digital integrated circuits, simultaneous reduction of the propagation delay and power dissipation in bistable memory elements represents a challenging task. Design of a dynamic dual-edge-triggered flip flop (DETFF) is presented which is faster, employs fewer transistors, and consumes less power than the standard static, master-slave flip flop. The proposed topology for the dynamic DETFF combines a pair of single-edge-triggered flip flops (FFs) using a 2:1 multiplexer with one flip flop being triggered on the positive edge and the other on the negative edge of a true single-phase clock (TSPC). The use of only eight clocked transistors accounts for the low-power operation of the proposed DETFF. The performance of the proposed DETFF is compared with that of a static, master-slave D-type flip-flop in a 90nm CMOS technology based on SPICE simulations. Also, SPICE simulations indicate that operating with a 0.9-V power supply at a clock frequency of 16.7 GHz, the proposed DETFF exhibits an average clock-to-Q delay of 25 ps and consumes 146 µW in a 22nm CMOS technology. The performance of the proposed DETFF is also compared with those of a static DETFF employing C-elements and a static TSPC DETFF capable of near-threshold operation in nanometer CMOS technologies.

Keywords

Main Subjects

References

[1] Bhattacharjee, Pritam, and Alak Majumder. "A variation-aware robust gated flip-flop for power-constrained FSM application." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950108.
[2] Sabu, Neethu Anna, and K. Batri. "Design and analysis of power efficient TG based dual edge triggered flip-flops with stacking technique." Journal of Circuits, Systems and Computers 29, no. 08 (2020): 2050123.
[3] Huang, Zhengfeng, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, and Yingchun Lu. "Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements." Journal of Circuits, Systems and Computers 31, no. 13 (2022): 2250231.
[4] Asyaei, Mohammad. "Low-Power Register File Design in 90nm CMOS Technology." Journal of Modeling in Engineering 16, no. 54 (2017): 69-81. (in Persian) 
[5] Pal, Ajit. Low-power VLSI Circuits and Systems. 1st ed., Springer, New Delhi, India, 2015.
[6] Kim, Chulwoo, and Sung-Mo Kang. "A low-swing clock double-edge triggered flip-flop." IEEE Journal of Solid-State Circuits 37, no. 5 (2002): 648-652.
[7] Nagarajan, P., N. Ashok Kumar, and P. Venkat Ramana. "Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems." International Journal of Wavelets, Multiresolution and Information Processing 18, no. 01 (2020): 1941009.
[8] Lee, Yongmin, Gicheol Shin, and Yoonmyung Lee. "A fully static true-single-phase-clocked dual-edge-triggered flip-flop for near-threshold voltage operation in IoT applications." IEEE Access 8 (2020): 40232-40245.
[9] Bonetti, Andrea, Adam Teman, and Andreas Burg. "An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1850-1853. IEEE, 2015.
[10] Singar, Sumitra, N. K. Joshi, and P. K. Ghosh. "A Glitch‐Free Novel DET‐FF in 22 nm CMOS for Low‐Power Application." Journal of Nanotechnology 2018, no. 1 (2018): 2934268.
[11] Singar, Sumitra, N. K. Joshi, and P. K. Ghosh. "Low Glitch DET-FF for Low Power Integrated Applications." In 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN), pp. 1030-1034. IEEE, 2019.
[12] Rajmohan, M., K. Sakthidasan Sankaran, and T. Rasagna. "Design of 4-Bit Dual Edge Triggered Counter using Quantum DOT Cellular Automata." In 2020 International Conference on Communication and Signal Processing (ICCSP), pp. 1467-1471. IEEE, 2020..
[13] Ji-Ren, Yuan, Ingemar Karlsson, and Christer Svensson. "A true single-phase-clock dynamic CMOS circuit technique." IEEE Journal of Solid-State Circuits 22, no. 5 (1987): 899-901.
[14] Rajabi, Maryam, Shahriar Jamasb, and Yousef Ganjdanesh. "Low-power, Dynamic, D-type Flip-Flops for Biomedical Implant Devices." Cumhuriyet Science Journal 36, no. 3 (2015): 21-28.
Journal of Modeling in Engineering
Volume 23, Issue 82
October 2025
Pages 143-156

Files

History

  • Receive Date: 18 July 2022
  • Revise Date: 17 March 2024
  • Accept Date: 30 November 2024

Share

How to cite

Statistics