Nasibeh Siadaty,Karim Mohammadi   Iran University of Science & Technology - Department of Electrical engineering    Abstract  Increase of design complexity of assembled circuits, and on the other hand necessity to separation the activity of computational and communicational parts in today chips, drives design way to terminals base on network on chips.As technology scales, fault tolerance is becoming a key concern in on-chip communication.Consequently, this work examines fault tolerant communication algorithms for use in the NoC domain, and compares them in terms of the functional parameters.  Then introduces a algorithm with purpose of encounter permanent and transient faults with appropriate functional levels. In this manner that against of permanent faults that exist structural in network on chip, packet has a expectation ability and finally return source to find another path and information bits are protected by a cyclic redundancy code (CRC) and Switch-to-Switch Error Control Policies (link level), against of transient faults. with appearance of fault, because of existence several sorts of the same packet in network, it will be discarded. R eceiver doesnât need to request of retransmission because it will receive redundant of packet from the same or another path.
Siadaty, N., & Mohammadi, K. (2008). Design and Simulation of Fault Tolerant Algorithms in Network-on-Chip. Journal of Modeling in Engineering, 7(16), -. doi: 10.22075/jme.2017.1524
MLA
Nasibeh Siadaty; Karim Mohammadi. "Design and Simulation of Fault Tolerant Algorithms in Network-on-Chip". Journal of Modeling in Engineering, 7, 16, 2008, -. doi: 10.22075/jme.2017.1524
HARVARD
Siadaty, N., Mohammadi, K. (2008). 'Design and Simulation of Fault Tolerant Algorithms in Network-on-Chip', Journal of Modeling in Engineering, 7(16), pp. -. doi: 10.22075/jme.2017.1524
VANCOUVER
Siadaty, N., Mohammadi, K. Design and Simulation of Fault Tolerant Algorithms in Network-on-Chip. Journal of Modeling in Engineering, 2008; 7(16): -. doi: 10.22075/jme.2017.1524
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