Improvement in the Performance of Tunneling Carbon Nanotube Field Effects Transistor in Presence of Underlap

Document Type : Power Article

Authors

1 Electrical engineering department, Energy faculty, Kermanshah University of Technology

2 Electrical engineering department, Engineering Faculty, Lorestan University

Abstract

Underlap between gate and drain/source area is one of the important items non-ideal effects in the device manufacturing process in the nanometer scale. In this paper, for the first time, the effect of underlap between the gate and drain/source area for tunneling carbon nanotube field effects transistor is investigated. To simulate the device, self- consistent solution of Schrodinger and Poisson equations and Non-equilibrium Green’s Function method have been employed. The function of the device is evaluated in terms of the on-state current, off-state current, current ratio, sub-threshold swing, delay time, and the power delay product. The simulation results show that the underlap effect improves some of the device characteristics and has some adverse effects on other characteristics. In the case where the length of underlap area is optimally chosen, the device performance will be improved considerably. Simulation results indicate that underlap significantly reduces the off-state current and thus reduces band-to-band tunneling and ambipolar behavior of the device. Also, the underlap effect by improving the power delay product parameter is a suitable option for low power applications compared with the conventional structure.

Keywords

References

[1] S.O. Koswatta, D.E. Nikonov, and M. S. Lundstrom, "Computational study of carbon nanotube p-i-n tunnel FETs", IEEE International Electron Devices Meeting, IEDM Technical Digest, December 2005, pp. 518–521.
[2] M.J. Lee, and W.Y. Choi, "Effects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors", IEEE Electron Device Letters, Vol. 33, No. 10, October 2012, pp. 1459–1461.
[3] A. Naderi, and S.A. Ahmadmiri, "Attributes in the Performance and Design Considerations of Asymmetric Drain and Source Regions in Carbon Nanotube Field Effect Transistors: Quantum Simulation Study", ECS Journal of Solid State Science and Technology, Vol. 5, No.7, May 2016, pp.M63–M68.
[4] A. Naderi, and P. Keshavarzi, "The effects of source/drain and gateoverlap on the performance of carbon nanotube field effect transistors", Superlattices and Microstructures, Vol. 52, No. 5, November 2012, pp. 962–976.
[5] A. Naderi, and M. Ghodrati, "Improving band-to-band tunneling in a tunneling carbon nanotube field effect transistor by multi-level development of impurities in the drain region", The European Physical Journal Plus, Vol. 132, December 2017.
[6] D.L. Pulfrey, and L. Chen, "Comparison of p-i-n and n-i-n carbon nanotube FETs regarding high-frequency performance", Solid-State Electron, Vol. 53, No. 9, September 2009, pp. 935–939.
[7] L. M. Peng, Z. Zhang, and S. Wang, "Carbon nanotube electronics: recent advances", Materials Today, Vol. 17, No. 9, November 2014, pp. 433–442.
[8] A.K. Sharma, R. Gupta, and A. Sharma, "Comparison of the Proposed Device With Conventional Gate All Around Tunnel Field Effect Transistor GAA-TFET", International Journal of Science, Technology and Management, Vol. 03, No. 09, September 2014, pp. 1537–2394.
[9] A. Rahman, J. Guo, and S. Datta, "Theory of Ballistic Nanotransistors", IEEE Transactions on Electron Devices, Vol. 50, No. 9, September 2003, pp. 1853–1864.
[10] W. Wang, X. Yang, N. Li, G. Xiao, S. Jiang, C. Xia, and Y. Wang, "Transport study of gate and channel engineering on the surrounding gate CNTFETs based on NEGF quantum theory", Journal of Computational Electronics, Vol. 13, NO. 1, March 2014, pp. 192–197.
[11] H. Wang, Sh. Chang, Y. Hu, H. He, J. He, Q. Huang, F. He, and G. Wang, "A Novel Barrier Controlled Tunnel FET", IEEE Electron Device Letters, Vol. 35, No. 7, May 2014, pp. 798–800.
[12] A. Naderi, and M. Ghodrati, "Cut Off Frequency Variation by Ambient Heating in Tunneling p-i-n CNTFETs", ECS Journal of Solid State Science and Technology, Vol. 7, No. 2, January 2018, pp. M6–M10.
[13] A. Naderi, and M. Ghodrati, "An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region", Turkish Journal of Electrical Engineering & Computer Sciences, Vol. 26, No. 5, August 2018, pp. 2335–2346.
[14] J. Guo, "Carbon nanotube electronics: Modeling, physics, and applications", Purdue University, August, 2004.
[15] A. Shaker, M. Ossaimee, A. Zekry, "Effect of asymmetrical double-pockets and gate-drain underlap on Schottky barrier tunneling FET: Ambipolar conduction vs. high frequency performance", Superlattices and Microstructures, Vol. 96, 2016, pp. 179–190.
224 بهبود عملکرد ترانزیستور اثر میدانی نانولوله کربنی تونلی در حضور ناهمپوشانی
مجله مدل سازی در مهندسی سال هفدهم، شماره 59 ، زمستان 1398
[16] A. Shaker, M. Ossaimee, A. Zekry, M. Abouelatta, "Influence of Gate Overlap Engineering on Ambipolar and High Frequency Characteristics of Tunnel-CNTFET", Superlattices and Microstructures, Vol. 86, October 2015, pp. 518–530.
[ 17 [ بهروز عبدی تهنه و علی نادری، "ساختار جدید ترانزیستور اثر میدانی نانو لوله کربنی تونلزنی با دوپینگ خطی در ناحیه درین:
شبیهسازی عددی کوانتومی"، نشریه مدلسازی در مهندسی، دوره 16 ، شماره 52 ، بهار 1397 ، صفحه 109 - 117 .
]18[ علی اصغر اروجی، اکرم عنبر حیدری و زینب رمضانی،" ترانزیستور اثر میدان فلز- نیمه هادی با ناحیه بدون ناخالصی در طرف درین
برای اصلاح چگالی حاملها و کاربردهای توان بالا"، نشریه مدلسازی در مهندسی، دوره 13 ، شماره 43 ، زمستان 1394 ، صفحه 121 -
127 .
]19[ میثم زارعی و مهسا مهراد، " تکنیک نوین برای کاهش اثر خودگرمایی در ترانزیستورهای اثرمیدان با سورس و درین گسترده شده"،
نشریه مدلسازی در مهندسی، دوره 16 ، شماره 53 ، تابستان 1397 ، صفحه 149 - 155 .
Journal of Modeling in Engineering
Volume 17, Issue 59
December 2019
Pages 215-224

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History

  • Receive Date: 11 April 2019
  • Revise Date: 17 June 2019
  • Accept Date: 19 June 2019

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