Introduction of the structure, modeling and analysis of junctionless heterostructure Si/Si1-xGex transistor

Document Type : Power Article

Authors

1 Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran

2 Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran

3 Department of Electrical Engineering, Islamic Azad University (Central Branch), Tehran, Iran

Abstract

In Junctionless transistors, the source-channel-drain doping is of the same type and level, hence, the process of making Junctionless transistors is easier than inverting mode transistor. Despite this benefit, reducing the transconductance of Junctionless transistors due to reduced carrier velocity makes the operation of this type of transistor difficult for analog, radio frequency and high frequency noise usages. An effective method that increases the trans-conductance of Junctionless transistors without reducing efficiency is using a heterogeneous structure in the channel. In the present article, using Si and Si1-xGex materials in the channel is proposed and modeled so as to enhance the transconductance of Junctionless transistor. The special structure of the proposed transistor, called JL-Si / Si1-xGex, eliminates the intervalley scattering between valleys of ∆2 and ∆4. This increases the velocity of the electron and consequently enhances the transconductance. The outcomes of the modelling of the proposed JL-Si / Si1-xGex heterostructure transistor indicate the maximum transconductance of 2.5 mS / um, which increases 50% compared to similar silicon transistor. Moreover, calculations which are extracted from modelling demonstrate that the proposed JL-Si / Si1-xGex transistor has a unity gain cutoff frequency of 750 GHz, minimum noise figure of 65.0 dB, and an available gain of 28.5 dB. The parameters of cut-off frequency, minimum noise figure and available gain of the proposed JL-Si / Si1-xGex transistor have been improved by 34%, 62.5% and 53%, respectively, compared to the JL-Si transistor with similar dimensions. The proposed device can be suitable candidate for RFIC applications.

Keywords

References

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Journal of Modeling in Engineering
Volume 21, Issue 72
March 2023
Pages 109-121

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History

  • Receive Date: 24 May 2022
  • Revise Date: 16 November 2022
  • Accept Date: 26 November 2022

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