کاهش مؤلفه ناخواسته مرجع در فرکانس سازهای عدد صحیح

نوع مقاله : مقاله پژوهشی

نویسندگان

گروه برق، مؤسسه آموزش عالی کارون، اهواز، ایران

چکیده

فرکانس‌ساز نقش مهمی را در فرستنده وگیرنده‌های‌ RF ایفا می‌کند. غیرایده‌آل بودن مدار تلمبه‌ی بار و آشکارساز فاز- فرکانس مؤلفه‌های ناخواسته‌ای در خروجی فرکانس‌ساز ایجاد می‌‌‌کند. در این مقاله یک روش جدید برای کاهش مؤلفه ناخواسته مرجع در فرکانس‌ساز پیشنهاد شده است. سیستم کاهش مؤلفه ناخواسته مرجع بین تلمبه‌ی بار و فیلتر پایین گذر به‌منظور کاهش دامنه ریپل‌های متناوب روی ولتاژ کنترل، اسیلاتور کنترل شده ولتاژ (VCO) قرار گرفته است. توسط کاهش دادن دامنه ریپل‌های متناوب، مؤلفه ناخواسته مرجع تضعیف می‌شود. ساختار پیشنهادی نیاز برای کاهش پهنای‌باند و کاهش گین VCO برای سرکوب مؤلفه ناخواسته مرجع را حذف می‌کند. برای نشان دادن اثرات ساختار پیشنهادی یک مولد فرکانسی GHz 22/2- 06/2 و کلاک مرجع MHz20 طراحی شده است و شبیه‌سازی post-layout با استفاده از فناوری180 نانومتر CMOSانجام شده است. سطح مؤلفه ناخواسته مرجع در فاصله 20 MHz مقدارش dBc84/85- و در فاصله 200 KHz مقدار نویز فاز dBc/Hz108- بدست آمده است و زمان قفل ساختار پیشنهادی حدود 3 /2 بدست آمده است.

کلیدواژه‌ها

موضوعات

عنوان مقاله [English]

Reduction of Reference Spur in the Integer-N Frequency Synthesizers

نویسندگان [English]

  • Sakineh Jahangirzadeh
  • Atefeh Rahimifar
Department of Electrical Engineering, Karoon Higher Education Institute, Ahvaz, Iran
چکیده [English]

The frequency generator plays an important role in RF transmitters and receivers. The non-ideality of the circuit of the charge pump and the phase-frequency detector creates spurious tones in the Frequency synthesizer output. In this paper, a new technique is proposed to reduce the reference spur in frequency synthesizer. A spur reduction system is inserted between the charge pump and the low pass filter to reduce the amplitude of periodic ripples on the VCO control voltage. By lowering the amplitude of the periodic ripple on the VCO control voltage, we managed to lower the reference spur. The introduced technique removes the necessity to decrease bandwidth and VCO gain reference spur suppressing. To demonstrate the effectiveness of the proposed structure, a 2.06 – 2.22 GHz frequency synthesizer was used and the 180-nm CMOS technology was used for post-layout simulation. The proposed frequency synthesizer represents the reference spur of -85.84 dBc at 20 MHz offset and phase noise of -108dBc/Hz at 200 kHz offset frequency also it is locked after 2.3us.

کلیدواژه‌ها [English]

  • Integer-N frequency synthesize
  • Reference spur
  • Voltage controlled oscillator (VCO)

مراجع

[1] T.H. Lin, and W.J. Kaiser. " A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop. " IEEE Journal of Solid-State Circuits 36, no. 3 (2001): 424-431.
[2] S. Pellerano, S. Levantino, C. Samori, and A.L. Lacaita. " A 13.5-mW 5-GHz frequency synthesizer with dynamic-Logic frequency divider. " IEEE Journal of Solid-State Circuits 39, no. 2 (2004): 378-383.
[3] F. Herzel, G. Fischer, and H. Gustat. " An integrated CMOS RF synthesizer for 802.11a wireless LAN. " IEEE Journal of Solid-State Circuits 38, no. 10 (2003): 1767-1770.
[4] X. Gao, E. Klumperink, G. Socci, and M. Bohsali. "loops exploiting a sub-sampling phase detector. " IEEE Journal of Solid-State Circuits 45, no. 9 (2010): 1809-1821.
[5] X. Li, J. Zhang, Y. Zhang, W. Wang, H. Liu, and C. Lu. " A 5.7–6.0 GHz CMOS PLL with low phase noise and 68- dBc reference spur. " International Journal of Electronics and Communications, no. 85 (2018): 23-31.
[6] A. Kraal, F. Behbahani, and A.A. Abidi. " RF-CMOS oscillators with switched tuning. " Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, (1998): 555-558.
[7] D. Mandal, P. Mandal, and T.K. Bhattacharyya. " Spur reducing architecture of frequency synthesizer using switched capacitors. " IET Circuits Devices Systems 8, no. 4 (2014): 237-245.
[8] S. Bruss, and R. Spencer. " A 5-GHz CMOS type-II PLL with low KVCO and extended fine-tuning range. " IEEE Transactions on Microw 57, no. 8 (2009): 1978-1988.
[9] C.Y. Kuo, J.Y. Chang, and S.I. Liu. " A spur-reduction technique for a 5-GHz frequency synthesizer. " IEEE Transactions on circuits and systems 53, no. 3 (2006): 526-533.
[10] C.M. Hung, and K.O. Kenneth. " A fully integrated 1.5- V 5.5-GHz CMOS phase-locked loop. " IEEE Journal of Solid-State Circuits 37, no. 4 (2002): 521-525.
[11] Z. Bereber, S. Kameche, and E.Benlchelifa. " High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks. " Simulation Modelling Practice and Theory 95, (2019): 134-147.
[12] W.B. Wilson, U. Moon, K.R. Lakshmikumar, and  L.Dai. " A CMOS self-calibrating frequency synthesizer." IEEE Journal of Solid-State Circuits 35, no. 10 (2000): 1437-1444.
[13] T.C. Lee, and W.L. Lee. " A spur suppression technique for phase-locked Frequency synthesizers. " IEEE International Solid-State Circuits Conference (ISSCC), (2006): 2432-2433.
[14] H. Gan Ko, W. Bae, G. Jeong, and D.kyoon. " Reference Spur Reduction Techniques for a Phase-Locked Loop ". IEEE Access 7, (2019): 38035-38043.
[15] J. Sharma, and H. Krishnaswamy. " A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance. " IEEE Journal of Solid-State Circuits 45, no. 5 (2019): 1407-1424.
[16] C. Thambidurai, and N. Krishnapura. " On pulse position modulation and its application to PLLs for spur reduction n." IEEE Transactions on Circuits and Systems 58, no. 7 (2011): 1483-1496.
[17] J. Choi, W. Kim, and K. Lim. " A spur suppression technique using an edge interpolator for a charge-pump PLL. " IEEE Transactions on Circuits and Systems 20, no. 5 (2012): 969-973.
[18] J.F. Huang, J.L. Yang, and R.Y. Liu. " The 1-V 2.4 GHz low-spur Fractional-N frequency synthesizer chip design with exploiting randomly selected PFD and subsampling charge pump. " Microwave and Optical Technology Letters 57, no. 1 (2015): 61-66.
[19] C.F. Liang, H.H. Chen, and S.I. Liu. " Random Pulse Width Matching Frequency Synthesizer with Sub-Sampling Charge Pump." IEEE Transactions on Circuits and Systems 59, no. 12 (2012): 2815-2824.
[20] C.F. Liang, H.H. Chen, and S.I. Liu. " Spur-suppression techniques for frequency synthesizers. " IEEE Transactions on Circuits and Systems 54, no. 8 (2007): 653-657.
[21] M. Elsayed, A. Latif, and E. Sinencio. " A Spur-Frequency-Boosting PLL with a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS. " IEEE Journal of Solid-State Circuits 48, no. 9 (2013): 2104-2117.
[22] S. Jahangirzadeh, and A. Amirabadi. " Low spur frequency synthesizer using randomly shifted reference spur to higher frequencies. " International Journal of Electronics 107, no. 12 (2020): 2044-2067.
[23] N. Xi, F. Lin, T. Ye. " A Low-Spur and Intrinsically Aligned IL-PLL with Self-Feedback Injection Locked RO and Pseudo-Random Injection Locked Technique. " IEEE Transactions on Circuits and Systems, (2020): 1-10.
[24] D. Biswas, G.S. Javed, and K.S. Reddy. "5-GHz Integer-N PLL with spur reduction sampler”, IEEE Electronics Letters. " IEEE Electronics Letters 55, no. 23 (2019): 1217-1220.
[25] Y.W. Chen, Y.H. Yu, Y.J. Emery Chen. " A 0.18-𝜇m CMOS dual-band frequency synthesizer with spur reduction calibration. " IEEE Microwave and Wireless Components Letters 23, no. 10 (2013): 551-553.
[26] S. Jen Cheng, Y. Rong Qiu, and C. Hung Hong. "A 0.02mm2 Sub-Sampling PLL with Spur Reduction
Technique in 90nm CMOS Technology." 2023 International VLSI Symposium on Technology, (2023).
[27] Y. Liang, C. Chye Boon, C. Li, and Q. Chen. " A 28.8-to-43.2 GHz 79.8 fsrms Jitter and −78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration. " IEEE Transactions on Microwave Theory and Techniques 72, no. 5 (2024): 44392716-2733.
 
مدل سازی در مهندسی
دوره 23، شماره ویژه 81
جشن پنجاهمین سالگرد تاسیس دانشگاه سمنان- در حال تکمیل شدن
تیر 1404
صفحه 199-207

فایل ها

سابقه مقاله

  • تاریخ دریافت: 14 تیر 1402
  • تاریخ بازنگری: 13 مرداد 1403
  • تاریخ پذیرش: 01 مهر 1403

هم رسانی

ارجاع به این مقاله

آمار