عنوان مقاله [English]
نویسندگان [English]چکیده [English]
Metal Oxide Semiconductor Field Effect Transistor (MOSFET) plays a key role in electronic industry in recent years. Among MOSFETs, double gate (DG) transistor is an important device. During last decade, many efforts have been accomplished to improve the device properties. A new structure of the double gate (DG) transistor on SOI technology is proposed in this paper. In SOI technology, buried oxide as insulating layer has lower thermal conductivity than silicon and makes some problems for nano-scale MOSFETs. Incorporating a silicon window under the channel region and two spacers reduces maximum temperature of device. The simulation with ATLAS simulator shows that by optimizing the length and thickness of the silicon window, an acceptable device temperature would be achieved and makes the double gate structure more reliable for nano-scale applications at high temperature. Drain current, lattice temperature, electron mobility, hole density, threshold voltage, subthreshold swing and off current are improved in the new structure.
 Colinge J.P, 2004, Silicon-on-insulator technology: materials to VLSI, 3rd ed. Kluwer Academic Publishers.
 Mehrad M, Orouji A.A, 2011, A new nanaoscale and high temperature field effect transistor: bi level FinFET, Physica E, 44, 654-658.
 Orouji A.A, Mehrad M, 2014, Positive charges at buried oxide interface of RESURF: an analytical model for the breakdown voltage, Superlattices and Microstructures, 72, 336-343.
 Orouji A.A, Mehrad M, 2011, A new rounded edge fin field effect transistor for improving self-heating effects, Japanese J. Applied Phys., 50, 124303-124309.
Colinge J.P, 2004, Multi-gate SOI MOSFETs, Solid-State Electronics, 897-905.
 Zhou X, Lim K.Y, and Lim D, 1999, A simple and unambiguous definition of threshold voltage and its implication in deep-submicron MOS device modeling, IEEE Trans. Electron Devices, 46, 807-809.
 Mehrad M, Orouji A.A, 2010, Partially cylindrical fin field-effect transistor: a novel device for nanoscale applications, IEEE Trans. Device and Materials Reliability, 10, 271-275.
 Kranti A, Armstrong G.A, 2007, Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: novel design methodology for low-voltage analog applications, Microelectronic Engineering, 84, 2775-2784.
 Saxena M, Haldar S, Gupta M, Gupta R.S, 2004, Design consideration for novel device