طراحی رجیستر فایل توان- پایین در فناوری 90 نانومتر CMOS

نوع مقاله : مقاله برق

نویسنده

دانشگاه دامغان

چکیده

عمده توان مصرفی در رجیستر فایل‌های سریع مربوط به مسیرهای خواندن است که با استفاده از مدارهای دینامیکی پیاده سازی می‌شوند. از این‌رو، یک تکنیک مداری جدید در این مقاله پیشنهاد می‌شود که بدون کاهش چشمگیر سرعت و مصونیت در برابر نویز، توان مصرفی رجیستر فایل‌ها را کاهش می‌دهد. در مدار دینامیکی پیشنهادی، شبکه پایین‌کش به چند شبکه کوچکتر تقسیم می‌شود تا عملکرد مدار افزایش یابد. همچنین شبکه های پایین‌کش با استفاده از ترانزیستورهای NMOS پیش بار می‌شوند تا دامنه نوسان ولتاژ و در نتیجه توان مصرفی کم شود. با استفاده از مدار پیشنهادی، یک رجیستر فایل با 64 کلمه 32 بیتی، دو پورت برای خواندن و یک پورت برای نوشتن پیاده سازی می‌شود. رجیستر فایلهای مورد مطالعه با استفاده از نرم افزار HSPICE در تکنولوژی 90 نانومتر CMOS و با بکارگیری ترانزیستورهایی با ولتاژ آستانه کم شبیه سازی شدند. نتایج شبیه سازی برای رجیستر فایل‌ها نشان می‌دهند که تحت مصونیت در برابر نویز یکسان، توان مصرفی و تاخیر در رجیستر فایل پیشنهادی به ترتیب 37% و 36% نسبت به رجیستر فایل متداول کاهش یافته است.

کلیدواژه‌ها

موضوعات

عنوان مقاله [English]

Low-Power Register File Design in 90nm CMOS Technology

نویسنده [English]

  • Mohammad Asyaei
چکیده [English]

The main portion of the power consumption in high speed register files is related to read out paths which are implemented using the dynamic circuits. For this reason, a new dynamic circuit technique is proposed in this paper to reduce the power consumption of the register files without significant speed and noise immunity degradation. In the proposed dynamic circuit, the pull down network is partitioned to the some smaller pull down networks to increase the circuit performance. Moreover, pull-down networks are precharged using NMOS transistors to reduce the voltage swing and hence decrease the power consumption. A 64-word x 32-bit 2-read, 1-write ported register file is implemented using the proposed circuit technique. Simulation of register files are performed using HSPICE simulator in low-Vth 90-nm CMOS technology model. Simulation results demonstrate 37% and 36% reduction in power and delay respectively at the same noise immunity compared to the conventional register file.

کلیدواژه‌ها [English]

  • Register file
  • dynamic circuits
  • local and global bit lines
  • noise immunity

مراجع

   [1]      Krishnamurthy, K., Alvandpour, A., Balamurugan. G., Shanbhag. N. R., Soumyanath. K., Borkar. S. Y. (2002). “A 130-nm 6-GHz 256 ´ 32 Bit Leakage-Tolerant Register File”. IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, pp. 624-632.
   [2]      Intel Pentium 4 1.4 GHz Review, Part 1: Processor Architecture and Platform Overview pp. 1–11, Nov. 2000 [Online]. Available:http://www.xbitlabs.com/articles/cpu/display/pentium4-1400-1.html.
   [3]      Dadgour, H. F., Banerjee, K. (2010). “A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic OR Gates”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 11, pp. 1567 – 1577.
   [4]      Guan, X., Fei, Y. (2010). “Register File Partitioning and Compiler Support for Reducing Embedded Processor Power Consumption”. IEEE Transactions on Very Large Scale Integration (VLSI) syst., Vol. 18, No. 8, pp. 1248-1252, 2010.
   [5]      Gong, N., Wang, J., Sridhar, R. (2014). “Variation Aware Sleep Vector Selection in Dual Dynamic OR Circuits for Low Leakage Register File Design”, IEEE Transactions on Circuits and Systems, Vol. 61, No. 7, pp. 1970-1983, July 2014.
   [6]      Mostafa, H., Anis, M., Elmasry, M. (2011). “Novel Timing Yield Improvement Circuits for High-Performance Low-Power Wide Fan-In Dynamic OR Gates”. IEEE Transactions on Circuits and Systems, Vol. 58, No. 10, pp. 1785 – 1797.
   [7]      Alvandpour, A., Krishnamurthy, R., Sourrty, K., Borkar, S. Y. (2002). “A Sub-130-nm Conditional-Keeper Technique”. IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, pp. 633-638.
   [8]      Anis, M. H., Allam, M. W., Elmasry, M. I. (2002). “Energy-Efficient Noise-Tolerant Dynamic Styles for Scaled-Down CMOS and MTCMOS Technologies”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 2, pp. 71-78.
   [9]      Lih, Y., Tzartzanis, N., Walker, W. (2007). “A Leakage Current Replica Keeper for Dynamic Circuits”. IEEE Journal of Solid-State Circuits, Vol. 42, No. 1, pp. 48–55.
[10]      Mahmoodi-Meimand, H., Roy, K. (2004). “Diode-Footed Domino: A Leakage-Tolerant High Fan-In Dynamic Circuit Design Style”. IEEE Transactions on Circuits and Systems, Vol. 51, No. 3, pp. 495-503.
[11]     Peiravi, A., Asyaei, M., (2013). “Current-Comparison-Based Domino: A New Low-Leakage High Speed Domino Circuit for Wide Fan-In Gates”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.21, No. 51, pp. 934-943.
[12]     Asyaei, M. (2015). “A New Leakage-Tolerant Domino Circuit Using Voltage-Comparison for Wide Fan-In Gates in Deep Sub-Micron Technology”. Integration, the VLSI Journal, Vol. 51, pp. 61-71.
[13]      آسیایی، م. (1396)، "دومینو مبتنی بر مقایسه جریان ارتقاءیافته برای طراحی گیت‌های عریض توان پایین" مجله مهندسی برق دانشگاه تبریز، جلد 47، شماره 1.
[14]      Roy, K., Mukhopadhyay, S., Mahmoodi, H. (2003). “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”. Proceedings of the IEEE, Vol. 91, No. 2, pp. 305-327.
[15]      Rabaey, J., Chandrakasan, A., Nicolic, B. (2003). “Digital Integrated Circuits: A Design Perspective”. 2nd Edition, Englewood Cliffs, NJ: Prentice Hall.
[16]      Fisher, S., Teman, A., Vaysman, D., Gertsman, A., Yadid-Pecht, O., Fish, A. (2008). “Digital Subthreshold Logic Design–Motivation and Challenges”. IEEE 25th Convention of Electrical and Electronics Engineers, pp. 702-706.
[17]      Ding, D. L., Mazumder, P. (2004). “On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 9, pp. 910–925.
[18]      Asyaei, M., Peiravi, A. (2014). “Low Power Wide Gates for Modern Power Efficient Processors”. Integration, the VLSI Journal, Vol. 47, No. 2, pp. 272-283.
[19]      Z. Liu and V. Kursun, (2006). “Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies”. IEEE Transactions of Circuits and Systems. II, Vol. 53, No. 8, pp. 692–696.
[20]      Wang, L., Shanbhag, N. R. (2000). “An Energy-Efficient Noise-Tolerant Dynamic Circuit Technique”. IEEE Transactions on Circuits and Systems, Vol. 47, No. 11, pp. 1300-1306.
[21]      Peiravi, A., and Asyaei, M. (2012). “Noise-Immune Dual-Rail Dynamic Circuit for Wide Fan-In Gates in Asynchronous Designs”. IEEJ Transactions on Electrical and Electronic Engineering, Vol. 7, No. 6, pp. 613-621.
[22]      Agarwal, A., Roy, K., Krishnarnurthy, R. K., Borkar, S. (2004). “A 90nm 6.5GHz 128x64b 4-Read 4-Write Ported Parameter Variation Tolerant Register File”. Symposium on VLSI Circuits Digest of Technica1 Papers, pp. 386-387.
[23]      Hsu, S., Agarwal, A., Roy, K., Krishnarnurthy, R. K., Borkar, S. (2005). “An 8.3GHz Dual Supply/Threshold Optimized 32b Integer ALU-Register File Loop in 90nm CMOS”. International Symposium on Low Power Electronics and Design (ISLPED), pp. 103-106.
[24]      Yan, H., Liu, Y., Wang H. D., Hou, C. H. (2010). “A Low-Power 8-Read 4-Write Register File Design”. Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, pp. 178 - 181.
[25]      Hao, Y., Yan, L., Siliang, H., Donghui, W., Chaohuan, H. (2012). “A Low-Power Multi Port Register File Design Using a Low-Swing Strategy”. Journal of Semiconductors, Vol. 33, No. 3, pp. 35009:1-8.
[26]      Kim, C. H., Roy, K., Hsu, S., Alvandpour, A., Krishnamurthy, R. Borkar, S.  (2003). “A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits”. Svmoosium on VLSl Circuits Digest of Technical Papers, pp. 205-206.
[27]      Zhang, G., Yang, X., Zhang, Y., (2009). "Architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File". IEEE International Conference on Networking, Architecture and Storage, pp. 386 - 391.
[28]      Yang, S. C., Yang, H. I., Hwang, W., (2009). “A Micro-Watt Multi-Port Register File with Wide Operating Voltage Range”. IEEE International Workshop on Memory Technology, Design, and Testing, pp. 34-37.
[29]      Kim, C. H., Roy, K., Hsu, S., Krishnamurthy, R. Borkar, S. (2006). “A Process Variation Compensating Technique with an On-Die Leakage Current Sensor for Nanometer Scale Dynamic Circuits”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 6, pp. 646-649.
[30]      Daimary, I., Aneesh, M. (2015). “Design of Low Power Gates used in Register File and Tag Comparator”. International Journal of Computational Engineering & Management, Vol. 18, No. 2, pp. 1-6.
 
 
مدل سازی در مهندسی
دوره 16، شماره 54
مهر 1397
صفحه 69-81

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سابقه مقاله

  • تاریخ دریافت: 26 آذر 1395
  • تاریخ بازنگری: 04 آبان 1396
  • تاریخ پذیرش: 21 آبان 1396

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